The present invention is related to active circuits, in particular active inductors, which are incorporated in integrated circuits.
Active inductors have been described, for example in document U.S. Pat. No. 6,028,496, which is related to a device comprising two Operational Amplifiers (OPAMPS). The active inductor of this document includes an inverting amplifier of a common source (common emitter) type, which inversely amplifies an input signal and outputs the amplified signal as an output signal, a non-inverting amplifier of a common gate (common base) type, which non-inversely amplifies the output signal and the amplified signal as the input signal, a capacitor connected between the input signal and a reference signal, and a biasing portion for biasing the inverting amplifier and the non-inverting amplifier.
A general drawback of these existing active inductors is the fact that they all comprise at least two Operational Amplifiers, leading to a relatively high power consumption.
The present invention aims to provide an active inductor which consumes less power compared to the active inductors belonging to the current state of the art.
The present invention is related to an apparatus comprising an active circuit, the circuit synthesising an inductor, characterised in that the circuit comprises one Operational Amplifier.
According to a preferred embodiment, the invention is related to an apparatus comprising an active circuit, wherein the circuit comprises:
an Operational Amplifier with a non-inverting input terminal, an inverting input terminal, a non-inverting output terminal and an inverting output terminal,
a first resistor R1 and a first capacitance C1, connected in cascade between the inverting input terminal and a first output terminal of the active circuit,
a second resistor R1xe2x80x2, having the same resistance as R1, and a second capacitance C1xe2x80x2, having the same capacitance value as C1, connected in cascade between the non-inverting input terminal and a second output terminal of said the active circuit,
a third resistor R2 and a fourth resistor R3, connected in cascade between the non-inverting input terminal and the first output terminal of the circuit,
a fifth resistor R2xe2x80x2, having the same resistance as R2, and a sixth resistor R3xe2x80x2, having the same resistance as R3, the resistors R2xe2x80x2 and R3xe2x80x2 being connected in cascade between the inverting input terminal and the second output terminal of the circuit,
a seventh resistor Rx and a third capacitance Cx, connected in parallel, and coupled between the inverting output terminal and a common node of the third resistor R2 and the fourth resistor R3,
an eighth resistor Rxxe2x80x2, having the same resistance as Rx, and a fourth capacitance Cxxe2x80x2, having the same capacitance value as Cx, the resistor Rxxe2x80x2 and the capacitance Cxxe2x80x2 being connected in parallel, and coupled between the non-inverting output terminal and a common node of the fifth resistor R2xe2x80x2 and the sixth resistor R3 xe2x80x2,
a ninth resistor R4 connected between the inverting output terminal and the first output terminal of the circuit, and an tenth resistor R4xe2x80x2, connected between the non-inverting output terminal and the second output terminal of said circuit.
According to the preferred embodiment of the present invention, the resistance values of R4 and R4xe2x80x2 obey the following formula:   R4  =            R4      xe2x80x2        =                                        (                                          C1                ·                R1                            +                                                (                                                            2                      ⁢                      C1                                        -                    Cx                                    )                                ·                Rx                                      )                    ·          R3                +                  C1          ·          R1          ·          Rx                                      Cx          ·          Rx                -                  C1          ·          R1                    
According to a further embodiment, the invention is related to an apparatus wherein the inductor synthesised by said active circuit is tuneable. This may be realised by making the capacitors C1, C1xe2x80x2, Cx and Cxxe2x80x2 tuneable.
According to another embodiment, the ratio between C1 and Cx is constant.
According to another embodiment, the value Rx.Cx is greater than R1.C1.